The ZL50120 CESoP processor is a highly functional TDM to Packet bridging device providing both structured and unstructured circuit emulation services (CES) for T1 and E1 streams across a packet network based on MPLS, IP or Ethernet. The ZL50120 also supports unstructured J2, T3, E3 and STS-1. The device incorporates a range of powerful clock recovery mechanisms for each TDM stream and a dual Ethernet interface to aggregate data traffic with voice traffic.

Features & Benefits

• Circuit Emulation Services over Packet (CESoP)transport for MPLS, IP and Ethernet networks
• On-chip timing & synchronization recovery across a packet network
• On-chip dual reference Stratum 3 DPLL
• Grooming capability for Nx64 kbps trunking
• Fully compatible with Zarlink's ZL50110, ZL50111 and ZL50114 CESoP processors
• TDM Interface provides 128 bi-directional 64 Kbps channels or 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports
• Compatible with H.110, H-MVIP, ST-BUS backplane
• Direct connection to LIUs, framers, backplanes
• 100 Mbps MII interface for user data traffic
• 100 Mbps MII FE or 1000 Mbps GMII/TBI interface for network uplink
• Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413, IETF CESoPSN, IETF SAToP and user programmable
• Complies with ITU-T recommendation Y.1413, IETF PWE3 draft standards CESoPSN and SAToP and CES draft IAs from MEF and MFA
• On-chip packet memory with 128 ms jitter buffer

Related Products

Part Number	Description
ZL50119	64 Channel (2 T1/E1) CESoP Processor with dual Ethernet interface
ZL50118	32 Channel (1 T1/E1) CESoP Processor with dual Ethernet interface
ZL50117	128 Channel (4 T1/E1, 1 T3/E3/STS-1) CESoP Processor with single Ethernet interface
ZL50116	64 Channel (2 T1/E1) CESoP Processor with single Ethernet interface
ZL50115	32 Channel (1 T1/E1) CESoP Processor with single Ethernet interface
ZL50114	128 Channel (4 T1/E1) CESoP Processor with Dual Ethernet Interface
ZL50111	1024 Channel (32 T1/E1, 2 T3/E3) CESoP Processor with triple Ethernet interface
ZL50110	256 Channel (8 T1/E1) CESoP Processor with Dual Ethernet Interface

Documentation

• ZL50115-16-17-18-19-20-datasheet-may2008.pdf

Packaging Outline Drawings

• 105072-package-outline-jun2006.pdf

Design Manuals

• zl5011x-ethernet-bandwidth-estimator-aug2005.xls

Software Manuals

• zls5011-api-user-guide-feb2006.pdf

Application Notes

• zlan-239-appnote-apr2008.pdf
• zlan69-appnote-nov2004.pdf
• zlan64-appnote-nov2004.pdf
• zlan63-appnote-jun2005.pdf
• zlan61-appnote-may2005.pdf
• zlan-59-appnote-nov2004.pdf
• zlan-36-appnote-sept2006.pdf
• zlan134-appnote-jul2005.pdf
• zlan116-appnote-nov2004.pdf
• zlan115-appnote-sep2004.pdf

Product Previews

• zl50118-19-20-product-preview-feb2005.pdf

Downloads, Firmware and Drivers

BSDL Files:
• zl50120gag.bsd

IBIS Models:
• zl50120gag.ibs

PCB Design Files:
• zle50110-1-4-pcb-design-files.zip

Evaluation Boards

• zle50111-eval-board-description-nov2004.pdf

Typical Applications

• TDM traffic over packet networks
• Leased Line support over packet networks
• 3G Wireless Backhaul
• TDM over Cable
• TDM over WiFi (802.11x)
• TDM over WiMAX (802.16)
• FTTx (Fibre To The Premises)
• G/E PON (Passive Optical Networks)
• Layer 2 VPN services
• Customer-premise and Provider Edge Routers and Switches
• Ethernet and IP based IADs
• IP DSLAM, NG-DLC
• MDU/MTU

Product Packaging & Availability

Part Number	Package Type	Pin Count	Lead-Free Option	Shipping Option(s)	Lead Time(wks)	Status
ZL50120GAG	PBGA	324		Trays. Bake & Drypack	6-8 weeks	Production
ZL50120GAG2	PBGA	324	Pb-free-Tin/Silver/Copper	Trays. Bake & Drypack	6-8 weeks	Production

Packaging Information

• Soldering Profiles
• Moisture Sensitivity
• Shelf Life
• Reliability Data

Distribution & Representative Notices

PCN Notice:
• pcn-060518-1.pdf

Technical Support

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